Keysight M8050A 120 GBd Bit Error Ratio Tester (BERT)
The Keysight M8050A BERT enables success in high-speed SerDes chips and device deployments of 800G/1.6T Ethernet, OIF-CEI-112G/224G, PCIe, USB 3.2/4, and other leading technologies by providing an unmatched combination of 120 GBd signaling with uncompromised signal integrity.
The Keysight M8050A high-performance bit error ratio tester (BERT) platform enables accurate characterization of high-speed digital receivers used in next generation data center networks and server interfaces with symbol rates up to 120 GBd.
The M8050A high-performance BERT is part of the Keysight M8000 Series of BER test solutions. It can be combined with other hardware and software of the M8000 Series including modules from the M8040A platform such as the M8045A, M8046A, and M8054A modules.
Features:
- Added 1.6T Ethernet KP4 FEC encoding on M8042A pattern generator (8x200GE based on IEEE 802.3dj)
- Added USB 3.2 ×2 LTSSM support on M8042A pattern generator
- Added automatic de-emphasis optimization support using Keysight N1093A/B DCA-M
- Added DUT Control Interface (DCI) script examples for Keysight 1.6T functional BERTs such as Functional Interconnect Test Solutions FITS-8CH used as an error detector
- Extended maximum symbol rate for Keysight UXR used as an error detector up to 224 GBd
Specifications
| Number of Channels |
1 to 2 |
| Module Type |
Pattern Generator, Error Analyzer |
| Supported Data Rates |
120 Gbaud |
| Line Coding |
NRZ, PAM3, PAM4, PAM6, PAM8 |
