Terasic Comet A13 System on Module (SOM) and Evaluation Kit
The Comet A13 SOM is a compact, production-qualified System-on-Module based on the Altera Agilex™ 5 SoC FPGA; designed with ease of use and system integration in mind for edge AI and embedded applications.
By combining the FPGA fabric with ARM Cortex-A76/A55 processor cores and LPDDR4 memory (up to 2667 MTs), this SOM enables efficient data processing, real-time control, and system-level integration within a single platform. Its compute orientated architecture supports both data-intensive workloads and deterministic processing making it suitable for latency-sensitive applications.
The Comet A13 provides four transceivers up to 17.16 Gbps and 191 high-voltage IO pins supporting 1.8V, 2.5V, and 3.3V interfaces, allowing direct connection to a wide range of sensors, cameras, and industrial peripherals without additional interface logic or drivers. The dual 300-pin SEAM8 connectors provide high-speed signals and IO resources which simplifies carrier board design and enabling flexible system expansion.
Designed for deployment, the Comet A13 SOM reduces FPGA hardware design complexity and accelerates time-to-market, making it well suited for building system-level applications such as machine vision systems, robotics platforms, industrial automation, and real-time data acquisition systems.
Key Features:
- Processing System: Altera Agilex 5 E-Series SoC FPGA (A5ED013BB32AE4SCS) featuring FPGA fabric alongside Arm Cortex-A76 and Cortex-A55 cores.
- Memory: LPDDR4 memory onboard.
- Connectivity: 4 transceivers (up to 17.16 Gbps), 191 high-voltage I/O pins (supporting 1.8V, 2.5V, and 3.3V), and two 300-pin SEAM8 connectors.
Specifications:
| System |
|
| FPGA |
A5ED013BB32AE4SCS (Agilex 5 E-Series Device Group B) |
| Module Size |
60mm × 55mm |
| HVIO |
191 HVIO (3.3V ×16, 1.8/2.5/3.3V ×175) |
| HSIO |
72 HSIO (up to 12 LVDS RX and 24 LVDS TX/RX) |
| HPS IO |
48 HPS IO |
| Transceivers |
4 Transceivers |
| Interface |
Two SEAM8 Connectors (6×50 pin) |
| FPGA Side |
|
| Clock |
Fixed 50 /100MHz Clock |
| Memory |
LPDDR4-B: 1GB DDR4 with 16-bit data bus (no ECC) |
| FPGA I/O |
191-pin HVIO and 72-pin HSIO connected to SEAM8 connector |
| Transceivers |
4 transceiver and 1 reference clock connected to SEAM8 connectors |
| HPS Side |
|
| Memory |
LPDDR4-A: 4GB DDR4 with 32-bit data bus (no ECC). Shared with FPGA |
| HPS I/O |
48 HPS IO connected to SEAM8 connector |
| Storage |
8GB eMMC (Expandable) + eMMC SEL Switch |
| Carrier Board Features |
|
| Power Input |
12V DC Jack |
| Interface |
Two SEAF8 Connectors (6×50 pin) |
| FPGA Features |
LED ×1, SWITCH ×2, Button ×1 |
| HDMI |
HDMI Out (1080P) |
| Camera Interface |
22-pin Connector (4 Data Lane) for CSI2 Camera |
| GPIO Header |
One 3.3V 2×20 DE-GPIO Header |
| HPS Features |
MicroSD Socket |
| UART |
UART Port (Type-C Connector for Linux Terminal) |
| Ethernet |
Gigabit Ethernet PHY + RJ45 |
| Reset |
HPS Cold Reset Button |
| Indicators |
LED ×2, Button ×1 |
